T04 · D11 — Computer Architecture

1. Why this topic matters here

1.24 expected questions for one hour (ROI 0.992, fourth-best on the paper). It earns Tier 1 on cost efficiency rather than volume: two items in the recent corpus test it — a CPU system-bus question and an EIDE built-in-cache question — plus a third describing data transferred between the CPU and peripheral devices, which is the DMA concept.

Confidence is Medium rather than High: only two direct corpus items, and while aggregators list "computer fundamentals", none name architecture specifically. But an hour is cheap, and the content is almost entirely memorisation with no reasoning required.

2. Exactly what gets asked

Bus identification. Confirmed local item. Which bus carries what, and which are unidirectional versus bidirectional.

1. (b) 16 MB — Correct: (2^{24} = 16{,}777{,}216) bytes = 16 MB.

(c) 8 MB: this is (2^{23}), i.e., one fewer address line.
(a) 24 MB: this mistakenly treats the number of address lines as the memory size in MB.
(d) 4 MB: this is (2^{22}), i.e., two fewer address lines.

DMA. Confirmed local item, phrased as a scenario about transferring data between the CPU and peripherals. The defining fact is that DMA moves data without CPU involvement.

2. (a) Data bus — Correct: the data bus carries data to and from the CPU, memory, and I/O devices.

(d) Address bus: in the classic model it carries addresses unidirectionally from the CPU.
(c) Control bus: it carries control signals such as read/write, not the data being transferred.
(b) Power bus: it supplies electrical power, not data.

Address-bus width to memory size. n address lines address 2^n locations. A common calculation question.

3. (c) DMA — Correct: the DMA controller moves data between the device and memory while the CPU only sets up the transfer and handles completion.

(a) Programmed I/O: the CPU transfers each byte and polls device status.
(b) Interrupt-driven I/O: the CPU still transfers each byte/word when interrupted.
(d) Polling: the CPU repeatedly checks device status and does not transfer directly to memory.

Cache. Confirmed local item on a drive's built-in cache. Also hit ratio and average access time calculations, and the L1/L2/L3 hierarchy.

4. (a) 0.05 — Correct: miss ratio = (1 - \text{hit ratio} = 1 - 0.95 = 0.05).

(b) 0.95: this is the hit ratio, not the miss ratio.
(c) 1.95: this incorrectly adds the hit ratio to 1.
(d) 0.5: this is an arbitrary value unrelated to the given hit ratio.

Memory hierarchy ordering. Fastest to slowest, smallest to largest, most to least expensive.

5. (b) 1.6 GB/s — Correct: 64 bits = 8 bytes; (8 \times 200 \times 10^6 = 1.6 \times 10^9) bytes/s = 1.6 GB/s.

(c) 12.8 GB/s: this uses 64 bytes/transfer instead of 64 bits.
(a) 200 MB/s: this ignores the bus width.
(d) 800 MB/s: this uses 32 bits = 4 bytes/transfer instead of 64 bits.

RAM versus ROM, SRAM versus DRAM.

3. Concept notes

3.1 Von Neumann vs Harvard architecture

Aspect	von Neumann	Harvard
Memory	Single memory holds both instructions and data	Separate memories for instructions and data
Buses	One shared bus — a fetch and a data access cannot happen at once ("von Neumann bottleneck")	Separate instruction and data buses — both can be accessed in the same cycle
Word size	Instruction and data words are the same size	Instruction and data words can differ
Speed	Slower for a given technology	Faster, more parallel
Hardware cost	Simpler, cheaper	More hardware and pins
Instructions as data	Yes — program can be read/written as data	Not normally
Typical use	General-purpose CPUs	Microcontrollers, DSPs; also inside CPUs as split L1 instruction/data caches ("modified Harvard")

3.2 CPU components

Component	Function
ALU (Arithmetic Logic Unit)	Arithmetic (+, −, ×, ÷) and logic (AND, OR, NOT, XOR, shift, compare). Sets condition flags (zero, carry, sign, overflow) in the status/flag register (PSW)
CU (Control Unit)	Decodes the instruction, generates control signals that sequence the datapath, keeps timing. Does not process data
Registers	Fastest storage, inside the CPU

3.3 Common registers

Register	Full name	Holds
PC	Program Counter (Instruction Pointer)	Address of the next instruction to fetch
IR	Instruction Register	The instruction currently being decoded/executed
MAR	Memory Address Register	Address of the memory location to be read/written
MBR / MDR	Memory Buffer Register / Memory Data Register	Data read from or to be written to memory
AC	Accumulator	Intermediate ALU result (in accumulator machines)
SP	Stack Pointer	Address of the top of the stack
PSW / Flags	Program Status Word	Condition flags, interrupt-enable, mode bits
GPR / IX	General-purpose / Index registers	Operands and addresses

MAR and MBR sit on the CPU–memory boundary: every memory access goes address → MAR, data → MBR.

3.4 Fetch–decode–execute cycle

Step	Actions
1. Fetch	`MAR ← PC`; issue memory read; `MBR ← M[MAR]`; `IR ← MBR`; `PC ← PC + 1` (increment, or add instruction length)
2. Decode	CU examines the opcode in IR, determines the operation and how to locate operands
3. Execute	Operands read from registers or memory; ALU performs the operation; address calculation for branches/loads/stores
4. Store / Writeback	Result written to a register or memory; flags updated; repeat from step 1

Interrupts are normally checked between instructions (at the end of the cycle), not mid-instruction.

3.5 The three system buses

Bus	Carries	Direction	Width determines
Address bus	Address of the memory location or I/O port to access	Unidirectional (CPU → memory/I/O)	Number of addressable locations: n lines → 2^n locations
Data bus	The actual data or instruction word	Bidirectional	Number of bits transferred per cycle (word size)
Control bus	Read, Write, Memory/IO select, clock, Reset, Interrupt Request, Interrupt Acknowledge, Bus Request/Grant	Mixed: read/write/clock/reset are CPU → devices; interrupt request, ready, bus request are device → CPU	— (signals, not capacity)

Address-bus width examples (one address = one addressable unit, conventionally a byte):

Address lines n	Locations = 2^n	Byte-addressable capacity
16	65,536	64 KiB
20	1,048,576	1 MiB
32	4,294,967,296	4 GiB

If a machine is word-addressable instead, 2^n addresses cover 2^n × (word size in bytes).

3.6 Instruction pipelining and hazards

Pipelining overlaps the stages of different instructions (classic 5 stages: IF, ID, EX, MEM, WB). It raises throughput, not the latency of one instruction. A k-stage pipeline ideally gives up to k× speedup and near 1 instruction per clock once full. Filling and draining the pipeline costs a few cycles on each restart.

Hazard	Cause	Typical fix
Structural	Two instructions need the same hardware in the same cycle (e.g. one memory port for fetch and data)	Duplicate the resource; separate instruction/data caches; stall
Data	An instruction needs a result not yet produced — RAW (read after write) is the common one; WAR and WAW occur with out-of-order execution	Forwarding/bypassing, stall (bubble), compiler scheduling, register renaming
Control	A branch means the next instruction fetch address is unknown	Branch prediction, delayed branch, flush and stall on misprediction

3.7 CISC vs RISC

Aspect	CISC	RISC
Instruction set	Large, many complex instructions	Small, simple, fixed-length instructions (mostly)
Instruction length	Variable	Fixed
Cycles per instruction	Often multiple	Mostly one
Addressing modes	Many	Few
Registers	Fewer	Many, load/store style
Memory access	Operands can come from memory	Only load/store touch memory
Control unit	Microprogrammed	Hardwired
Pipelining	Harder	Easier
Code size	Smaller	Larger
Compiler effort	Low	High
Power	Higher	Lower
Examples	x86, older mainframes	ARM, MIPS, RISC-V, Power

3.8 Memory hierarchy (top to bottom: fastest, smallest, costliest per bit)

Level	Technology	Typical size order	Typical access time	Managed by
Registers	Flip-flops	Bytes	Sub-nanosecond	Compiler
L1 cache	SRAM	Tens of KB	~1 ns	Hardware
L2 cache	SRAM	Hundreds of KB – few MB	Few ns	Hardware
L3 cache	SRAM	Up to tens of MB (often shared)	~10 ns	Hardware
Main memory	DRAM	GB	Tens of ns	OS
Secondary	SSD / HDD	Hundreds of GB – TB	µs (SSD) to ms (HDD)	OS
Tertiary	Magnetic tape, optical jukebox	TB and above	Seconds, often offline	Backup software / operator

Rule: as you move down, capacity and access time increase; cost per bit and speed decrease.

3.9 Cache memory

Why it exists: CPU speed outgrew DRAM speed. A small fast SRAM between CPU and main memory holds recently used blocks so most accesses never reach DRAM.

Locality of reference

Temporal: a location accessed once is likely to be accessed again soon (loops).
Spatial: locations near an accessed address are likely to be accessed soon (arrays, sequential code) — the reason data is copied in blocks/lines, not single words.

Term	Meaning
Hit	Requested block is in cache
Miss	Not in cache; the block is fetched from the next level and the line is filled
Hit ratio h	h = (number of hits) / (total accesses)
Miss ratio	1 − h
L1	Smallest, fastest, per-core, split into I-cache and D-cache
L2	Larger, slower, per-core or per-cluster
L3	Largest, slowest, usually shared across cores

Average access time

T_avg = h × T_cache + (1 − h) × T_memory, where T_memory is the time for a memory access on a miss (including the cache lookup).
Equivalent form: T_avg = T_cache + (1 − h) × T_miss_penalty.
Speedup over always going to memory = T_memory / T_avg.
Example: T_cache = 5 ns, T_memory = 50 ns, h = 0.9 → T_avg = 0.9(5) + 0.1(50) = 9.5 ns.

Mapping techniques

Technique	Block placement	Search	Hardware cost	Conflict misses
Direct mapped	Each block goes to exactly one line: line = block number mod number of lines	Tag compared in one line only	Lowest, fastest	Highest
Fully associative	Any block may go in any line	Tag compared against every line in parallel	Highest (comparators + mux)	None (only capacity misses)
Set-associative (k-way)	Any block may go in any line of one set: set = block number mod number of sets; k lines per set	k tag comparisons in parallel	Between the two	Between the two; the usual compromise

Replacement policies (needed when a set is full): LRU, FIFO, random.

Write policies

	Write-through	Write-back (copy-back)
On a write hit	Write to cache and main memory	Write to cache only, set the dirty bit
Memory traffic	High — every write goes to memory	Lower — memory is updated only when a dirty line is evicted
Complexity	Simple	Needs a dirty bit and a write-back on eviction
Memory contents	Always up to date	Stale until eviction
Typical use	Small/simple caches	Modern CPU L1/L2

Write-miss policies: write-allocate (fetch the block, then write) usually pairs with write-back; no-write-allocate (write straight to memory) usually pairs with write-through.

3.10 Storage levels

	Primary	Secondary	Tertiary
Directly addressable by CPU	Yes	No — accessed via I/O and the OS	No
Role	Holds currently executing code and data	Online bulk storage of programs and files	Archive/backup, near-offline
Examples	Registers, cache, RAM, ROM	HDD, SSD, USB flash, SD card	Magnetic tape, optical jukebox, tape library
Cost per bit	Highest	Low	Lowest
Access time	ns	µs–ms	seconds, often with manual/robotic mounting

Volatile vs non-volatile

	Volatile	Non-volatile
Contents on power loss	Lost	Retained
Examples	RAM (SRAM, DRAM)	ROM, PROM, EPROM, EEPROM, flash, SSD, HDD, tape

Registers and cache are volatile but hold copies of data whose home is non-volatile storage.

RAM vs ROM

	RAM	ROM
Full form	Random Access Memory	Read Only Memory
Read/write	Read and write	Mainly read; contents fixed at manufacture or programmed later
Volatility	Volatile	Non-volatile
Use	Main memory, cache	Firmware, BIOS, boot code, embedded constants

SRAM vs DRAM

	SRAM	DRAM
Cell	6 transistors (flip-flop)	1 transistor + 1 capacitor
Refresh	Not required	Required periodically (charge leaks)
Speed	Faster	Slower
Density	Lower	Higher
Cost per bit	Higher	Lower
Power	No refresh power, but continuous leakage	Refresh power
Use	Cache, registers	Main memory

ROM types

Type	Programmed	Erasable	Erase method / granularity
Mask ROM	At manufacture	No	—
PROM	Once, by the user with a programmer	No	—
EPROM	By the user with a programmer	Yes	UV light through a quartz window; whole chip
EEPROM	Electrically, in circuit	Yes	Electrically; byte/word level
Flash	Electrically, in circuit	Yes	Electrically; block level — faster and denser than EEPROM

Flash is the technology behind SSDs, USB drives, memory cards and modern firmware ROM.

3.11 I/O transfer methods

Method	Who moves the data	CPU role	Speed	Weakness
Programmed I/O (polling)	CPU	CPU repeatedly reads the device status register until ready, then transfers each word	Slowest	Busy-waiting burns CPU cycles
Interrupt-driven I/O	CPU	CPU transfers the data but is not tied up waiting; the device raises an interrupt when ready, and the CPU runs the handler	Medium	One interrupt per word/byte; context-save overhead
DMA	DMA controller	CPU only sets up source, destination, count and direction, then is interrupted once at completion	Fastest	Requires a bus master / controller

DMA (Direct Memory Access) — a DMA controller transfers data between a peripheral and memory without the CPU moving each word. The CPU is free to execute other instructions during the transfer; it is notified by an interrupt when the whole block is done.

Cycle stealing — the DMA controller becomes bus master and takes one memory cycle at a time from the CPU, which is briefly stalled, then continues. Transfers interleave with CPU work; the CPU slows slightly. In burst mode the DMA controller holds the bus for the whole block — faster transfer, longer CPU stall.

Interrupts and the interrupt vector table — a device signals the CPU through an interrupt request line. The CPU finishes the current instruction, saves the return address and flags (usually on the stack), looks up the handler address in the interrupt vector table (an array indexed by interrupt number, holding the ISR entry point for each interrupt), jumps there, runs the handler, then executes a return-from-interrupt. Interrupts may be maskable or non-maskable (NMI) and have priorities; interrupt latency is the delay before the handler starts.

3.12 PATA/EIDE vs SATA and drive buffers

Aspect	PATA / EIDE	SATA
Signalling	Parallel, 16 data bits	Serial, one bit per direction (differential pairs)
Connector / cable	40-pin, 40- or 80-conductor ribbon; ~45 cm limit	7-pin thin cable; ~1 m, better airflow
Devices per channel	2, configured as master/slave by jumpers	1 per port (point-to-point); no master/slave
Transfer rate	Up to ~133 MB/s (UDMA/133)	1.5 / 3 / 6 Gbps link rates (≈150 / 300 / 600 MB/s), later 16 Gbps
Features	No command queueing	NCQ (native command queueing), hot-plug, lower voltage

EIDE ("Enhanced IDE") is a PATA mode set with higher transfer rates — the terms overlap.

Drive cache / buffer — a small DRAM area on the drive's own controller. It holds recently read sectors so repeated reads are served without touching the platters or NAND, and it queues and reorders pending writes so the medium is written in efficient order. It improves latency and throughput only; it does not make the drive faster than the medium for first-time reads.

4. Must-memorise block

Registers

Register	Holds
PC	Address of the next instruction
IR	The current instruction
MAR	Address of the memory location being accessed
MBR / MDR	Data read from / to be written to memory
AC	Accumulator — ALU result
SP	Top of stack
PSW	Flags / status

Fetch order: PC → MAR → memory read → MBR → IR → PC + 1 → decode → execute → writeback.

Three buses

Bus	Carries	Direction
Address	Location address	Unidirectional (CPU out)
Data	Data/instruction word	Bidirectional
Control	Read, Write, Clock, Reset, Interrupt Request/Ack, Bus Request/Grant	Mixed

Addressing: n address lines → 2^n locations. 16 → 65,536 (64 KiB) · 20 → 1,048,576 (1 MiB) · 32 → 4,294,967,296 (4 GiB).

Pipelining: k stages → up to k× throughput, not k× lower latency. Hazards = structural, data (RAW/WAR/WAW), control (branch). Fixes = forwarding, stall, branch prediction, extra hardware.

CISC vs RISC: CISC = many complex variable-length instructions, memory operands allowed, microprogrammed, fewer registers, smaller code, higher power. RISC = few simple fixed-length instructions, load/store only, hardwired, many registers, easier pipelining, lower power.

Memory hierarchy (fast/small/costly → slow/large/cheap): Registers → L1 → L2 → L3 → Main memory (DRAM) → Secondary (SSD/HDD) → Tertiary (tape).

Cache: exists because of the CPU–DRAM speed gap. Locality = temporal (reuse) + spatial (neighbours) → blocks/lines.

Hit ratio h = hits / total accesses
T_avg = h·T_cache + (1 − h)·T_memory
T_avg = T_cache + (1 − h)·T_miss_penalty
Mapping: direct (1 line, cheapest, most conflicts) · fully associative (any line, costliest, no conflict misses) · set-associative (any line in one set, k-way, compromise)
Write: write-through = cache + memory every write, simple, memory always current · write-back = cache only + dirty bit, less traffic, memory stale until eviction

SRAM vs DRAM: SRAM = 6 transistors, no refresh, faster, lower density, costlier, used for cache. DRAM = 1 transistor + 1 capacitor, needs refresh, slower, denser, cheaper, used for main memory.

RAM vs ROM: RAM = read/write, volatile. ROM = read-mostly, non-volatile. ROM family: mask ROM → PROM (write once) → EPROM (UV, whole chip) → EEPROM (electrical, byte-level) → flash (electrical, block-level; SSDs, USB drives).

Three I/O methods

Method	Data moved by	Key point
Programmed I/O	CPU	Polls status, transfers each word, busy-waits
Interrupt-driven I/O	CPU	Device interrupts when ready; no polling; one interrupt per word
DMA	DMA controller	Moves data between a peripheral and memory without CPU involvement; CPU sets up and gets one completion interrupt

DMA defining property: the CPU does not move the data. Cycle stealing = DMA controller takes single memory cycles from the CPU (slight CPU slowdown); burst mode = holds the bus for the whole block.

Interrupts: device raises IRQ → CPU finishes current instruction → saves PC/flags → looks up handler address in the interrupt vector table (indexed by interrupt number) → runs ISR → return from interrupt.

Storage: primary = directly CPU-addressable (registers, cache, RAM, ROM) · secondary = online, OS-accessed (HDD, SSD, flash) · tertiary = archive/offline (tape, jukebox).

PATA/EIDE vs SATA: PATA = parallel, 40-pin ribbon, 2 drives per channel with master/slave, ≤133 MB/s, no NCQ. SATA = serial, 7-pin point-to-point, 1 device per port, 1.5/3/6 Gbps link, NCQ, hot-plug.

Drive cache/buffer: small DRAM on the drive controller; caches read sectors and queues/reorders writes to cut latency.

5. Worked examples

Example 1 — Address bus width to addressable memory

A processor uses a 32-bit address bus and is byte-addressable. It has a 16-bit data bus. What is the maximum directly addressable memory? If the same processor were word-addressable with 16-bit words, how many bytes could it address?

Reasoning:

Byte-addressable: each address selects 1 byte.
Number of addresses = (2^{32} = 4{,}294{,}967{,}296).
Memory = (4{,}294{,}967{,}296) bytes = 4 GB.
Word-addressable with 16-bit words: each address selects 2 bytes.
Number of words = (2^{32}).
Total bytes = (2^{32} \times 2 = 2^{33}) bytes = 8 GB.
The 16-bit data bus means 2 bytes can be transferred per bus cycle; it does not change the number of addressable locations.

Final answer: 4 GB byte-addressable; 8 GB if word-addressable with 16-bit words.

Example 2 — Bus bandwidth

A synchronous bus runs at 66 MHz and is 32 bits wide. What is its theoretical peak bandwidth? If each transfer takes one clock cycle, how long does it take to transfer 1 MB (1 MiB = (2^{20}) bytes)?

Reasoning:

Bus width = 32 bits = 4 bytes.
Frequency = 66 MHz = (66 \times 10^6) cycles/s.
Peak bandwidth = 4 bytes/cycle × (66 \times 10^6) cycles/s = (264 \times 10^6) bytes/s = 264 MB/s.
1 MiB = (2^{20}) bytes = 1,048,576 bytes.
Time = (1{,}048{,}576 \,/\, 264{,}000{,}000) s ≈ 0.00397 s.
0.00397 s = 3.97 ms.

Final answer: 264 MB/s; about 3.97 ms for 1 MiB.

Example 3 — Cache average access time

A cache has access time 8 ns, main memory has access time 120 ns, and the hit ratio is 0.92. Using (T_{\text{avg}} = h \cdot T_{\text{cache}} + (1-h) \cdot T_{\text{memory}}), find the average access time. If the cache is always checked first and main memory is accessed only on a miss, find the alternative average access time.

Reasoning:

Hit ratio (h = 0.92), miss ratio (= 1 - 0.92 = 0.08).
Weighted-average formula:
(0.92 \times 8 = 7.36) ns.
(0.08 \times 120 = 9.6) ns.
(T_{\text{avg}} = 7.36 + 9.6 = 16.96) ns.
Sequential-on-miss formula:
Hit takes 8 ns.
Miss takes cache lookup + main memory = (8 + 120 = 128) ns.
(T_{\text{avg}} = 0.92 \times 8 + 0.08 \times 128).
(= 7.36 + 10.24 = 17.6) ns.
Equivalent shortcut: (T_{\text{cache}} + (1-h) \cdot T_{\text{memory}} = 8 + 0.08 \times 120 = 8 + 9.6 = 17.6) ns.

Final answer: 16.96 ns using the weighted-average convention; 17.6 ns if the miss path includes the cache lookup.

Example 4 — DMA transfer time

A DMA controller transfers a 4 KB block from a disk to memory. The data bus is 16 bits wide. Each bus cycle transfers one 16-bit word and takes 100 ns. DMA setup overhead is 2 μs. Ignoring bus arbitration, how long does the transfer take?

Reasoning:

4 KB = 4096 bytes.
16 bits = 2 bytes per transfer.
Number of transfers = (4096 / 2 = 2048).
Transfer time = (2048 \times 100) ns = 204,800 ns.
204,800 ns = 204.8 μs.
Add setup overhead: (204.8 + 2 = 206.8) μs.
The CPU is not moving each word; it programs the DMA controller and is interrupted on completion.

Final answer: 206.8 μs.

Example 5 — EIDE built-in cache

An EIDE hard disk is advertised with a 2 MB built-in cache. What does this cache do, and which system component does it most directly benefit?

Reasoning:

EIDE (ATA/PATA) drives include a disk buffer cache on the drive’s controller.
It holds recently read sectors and buffers write data.
It lets the drive satisfy some host requests without a physical platter access.
It also absorbs speed differences between the drive and the host bus.
It is not the CPU’s L1/L2/L3 cache and does not store CPU instructions.
It is managed by the drive firmware, not by the CPU cache hierarchy.

Final answer: It is a drive-level data buffer that reduces effective disk access time; it benefits the I/O path and disk subsystem, not the CPU cache hierarchy.

6. Traps and gotchas

Trap	Why it catches people	How to avoid
Reading “32-bit” as data bus width when the question asks about addressable memory	Both buses are described in bits; addressable memory depends on address lines, not data lines	Separate the two: addressable locations = (2^{\text{address lines}}); data bus width affects transfer size per cycle
Assuming the address bus is bidirectional	Addresses are issued by the CPU in the classic system-bus model, so the bus is unidirectional	Remember: address bus CPU→memory/I/O; data bus bidirectional; control bus is a set of control lines
Confusing hit ratio with miss ratio	The question may give 90% hit and ask for miss-related time; 90% is not the miss fraction	Always compute miss ratio = (1 - \text{hit ratio}) before using it
Using (T_{\text{avg}} = h \cdot T_{\text{cache}} + (1-h) \cdot T_{\text{memory}}) when the miss path includes a cache lookup	Two common formulas differ by (h \cdot T_{\text{cache}}); the wording decides which one applies	If “cache checked first, memory only on miss,” use (T_{\text{cache}} + (1-h) \cdot T_{\text{memory}}); if miss penalty is main-memory time only, use the weighted average
Believing DMA needs no CPU at all	DMA bypasses the CPU for data movement, but the CPU programs the DMA controller and handles the completion interrupt	DMA removes per-byte CPU work, not setup/completion work
Treating interrupt-driven I/O as DMA	Both free the CPU from polling, but interrupt-driven I/O still has the CPU move each word	If the CPU is described as moving data, it is interrupt-driven; if a controller moves it, it is DMA
Calling the EIDE built-in cache a CPU cache	The word “cache” appears in both contexts, but EIDE cache is a disk buffer on the drive	Check what is being cached: CPU instructions/data → CPU cache; disk sectors → drive buffer
Mixing bits and bytes in bus bandwidth	32-bit bus = 4 bytes/cycle, not 32 bytes/cycle	Convert bits to bytes by dividing by 8 before multiplying by frequency

7. Practice questions

[Easy] (D11 — Address bus) A CPU has 24 address lines and is byte-addressable. What is the maximum directly addressable memory? (a) 24 MB (b) 16 MB (c) 8 MB (d) 4 MB
[Easy] (D11 — Bus types) Which bus carries data in both directions between the CPU, memory, and I/O devices? (a) Data bus (b) Power bus (c) Control bus (d) Address bus
[Easy] (D11 — DMA) Which I/O technique transfers data directly between an I/O device and memory without the CPU moving each byte? (a) Programmed I/O (b) Interrupt-driven I/O (c) DMA (d) Polling
[Easy] (D11 — Cache) If the cache hit ratio is 0.95, what is the miss ratio? (a) 0.05 (b) 0.95 (c) 1.95 (d) 0.5
[Medium] (D11 — Bus bandwidth) A 64-bit bus runs at 200 MHz. What is its theoretical peak bandwidth? (a) 200 MB/s (b) 1.6 GB/s (c) 12.8 GB/s (d) 800 MB/s
[Medium] (D11 — Cache average access time) A cache has access time 4 ns, main memory has access time 100 ns, and the hit ratio is 0.90. Using (T_{\text{avg}} = h \cdot T_{\text{cache}} + (1-h) \cdot T_{\text{memory}}), what is the average access time? (a) 104 ns (b) 14.0 ns (c) 10.4 ns (d) 13.6 ns

6. (d) 13.6 ns — Correct: (0.90 \times 4 + 0.10 \times 100 = 3.6 + 10 = 13.6) ns.

(b) 14.0 ns: this uses (T_{\text{cache}} + (1-h) \cdot T_{\text{memory}} = 4 + 10 = 14) ns.
(c) 10.4 ns: this comes from incorrect weighting or misplacing the decimal.
(a) 104 ns: this adds 4 ns and 100 ns without applying hit/miss probabilities.

[Medium] (D11 — DMA transfer time) A DMA controller transfers an 8 KB block using a 32-bit data bus. Each bus cycle takes 50 ns and transfers 32 bits. Ignoring overhead, how long does the transfer take? (a) 51.2 μs (b) 204.8 μs (c) 102.4 μs (d) 409.6 μs

7. (c) 102.4 μs — Correct: 8 KB = 8192 bytes; 32 bits = 4 bytes; (8192/4 = 2048) transfers; (2048 \times 50) ns = 102,400 ns = 102.4 μs.

(b) 204.8 μs: this assumes a 16-bit bus (2 bytes/transfer).
(a) 51.2 μs: this assumes a 64-bit bus (8 bytes/transfer).
(d) 409.6 μs: this assumes an 8-bit bus (1 byte/transfer).

[Medium] (D11 — EIDE cache) The built-in cache on an EIDE hard disk is primarily used to: (a) store CPU instructions (b) hold the BIOS (c) replace main memory (d) buffer disk data to improve performance

8. (d) buffer disk data to improve performance — Correct: the EIDE built-in cache is a drive-level buffer for recently read sectors and pending writes.

(a) store CPU instructions: that is the role of main memory and CPU cache, not the disk buffer.
(c) replace main memory: the drive cache is much smaller and does not act as the CPU’s working memory.
(b) hold the BIOS: the BIOS is stored in ROM/flash on the motherboard, not in the drive buffer.

[Medium] (D11 — I/O methods) Which I/O method keeps the CPU busy waiting and repeatedly checking device status? (a) DMA (b) Interrupt-driven I/O (c) Channel I/O (d) Programmed I/O (polling)

9. (d) Programmed I/O (polling) — Correct: the CPU repeatedly checks the device status and transfers data itself.

(a) DMA: the DMA controller transfers data, so the CPU does not poll.
(b) Interrupt-driven I/O: the CPU does other work until the device raises an interrupt.
(c) Channel I/O: a separate I/O processor handles transfers, not CPU polling.

[Medium] (D11 — Control bus) Which bus carries read/write and interrupt signals? (a) Address bus (b) Data bus (c) Control bus (d) Memory bus

10. (c) Control bus — Correct: the control bus carries command and status signals such as read, write, and interrupt requests.

(a) Address bus: it carries memory or I/O addresses.
(b) Data bus: it carries data between system components.
(d) Memory bus: this is a general term for the CPU-memory interconnect, not the specific bus for control signals.

[Hard] (D11 — Address bus and word size) A processor has 20 address lines. It is word-addressable with a word size of 32 bits. What is the maximum memory it can directly address? (a) 1 MB (b) 4 MB (c) 2 MB (d) 8 MB

11. (b) 4 MB — Correct: (2^{20}) words (\times) 4 bytes/word = 4,194,304 bytes = 4 MB.

(a) 1 MB: this assumes byte-addressable memory ((2^{20}) bytes).
(c) 2 MB: this assumes 16-bit words (2 bytes/word).
(d) 8 MB: this assumes 64-bit words (8 bytes/word).

[Hard] (D11 — Cache average access time) A cache has access time 5 ns, main memory has access time 100 ns, and the hit ratio is 80%. The cache is checked first, and main memory is accessed only on a miss. What is the average access time? (a) 25 ns (b) 24 ns (c) 20 ns (d) 105 ns

12. (a) 25 ns — Correct: (T_{\text{avg}} = T_{\text{cache}} + (1-h) \cdot T_{\text{memory}} = 5 + 0.2 \times 100 = 25) ns.

(b) 24 ns: this uses the weighted average (h \cdot T_{\text{cache}} + (1-h) \cdot T_{\text{memory}} = 0.8 \times 5 + 0.2 \times 100 = 24) ns.
(c) 20 ns: this computes only the miss penalty (0.2 \times 100).
(d) 105 ns: this adds 5 ns and 100 ns without applying hit/miss probabilities.

8. Resources

Resource	Type	Link	Free/Paid	Time	Why this one
IndiaBix — Computer science Q&A	Practice set	https://www.indiabix.com/computer-science/questions-and-answers/	Free	30 min	Strong on architecture-style recall MCQs
GfG — Operating systems	Tutorial series	https://www.geeksforgeeks.org/operating-systems/operating-systems/	Free	25 min	Use the memory-hierarchy and I/O sections
GfG — Complexity analysis guide	Article	https://www.geeksforgeeks.org/dsa/complete-guide-on-complexity-analysis/	Free	15 min	Background for cache and access-time reasoning
`question-banks/QB-T04-D11-computer-architecture.md`	Question bank	(this library)	Free	30 min	30 original questions including bus-width and hit-ratio calculations

All external links verified resolving 2026-09-16.

9. Self-check

[ ] I can name the CPU's components and the common registers (PC, IR, MAR, MBR, accumulator)
[ ] I can describe the fetch-decode-execute cycle step by step
[ ] I can state what each of the three buses carries and its directionality
[ ] I can compute addressable memory from address-bus width using 2^n
[ ] I can order the memory hierarchy by speed, size and cost
[ ] I can define temporal and spatial locality
[ ] I can compute a cache hit ratio and an average access time
[ ] I can compare SRAM and DRAM
[ ] I can state what DMA is and why it exists, in one sentence
[ ] I can name the three I/O transfer methods in order of CPU involvement
[ ] I scored 10/12 or better on the practice questions

10. Sources

Evidence	What it contributed
`extracted_questions.md` items 6, 40, 117	Data transferred between CPU and peripheral devices (DMA), CPU system bus, EIDE built-in cache
PrepInsta	Lists computer fundamentals under the technical assessment
`data/weightage.json` → subtopic `D11`	est_qs 1.24 · ROI 0.992 · Tier 1 · Medium confidence